1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly relates to a semiconductor integrated circuit device in which the loss of a high frequency signal in a signal line or spiral inductor thereof formed with a pad and metal is to be reduced.
2. Description of the Prior Art
In recent years, the remarkably wide use of cellular phones has rapidly increased the demand for semiconductor devices. The wide use functionally demands semiconductor devices that can operate also in the high frequency region. The development of technology which is directed to the reduction of the signal loss in the input/output port of the semiconductor device is proceeding in order to meet the demand. As such a prior art, a typical pad structure in CMOS technology is described in (R. Fujimoto, O. Watanabe, F. Fuji, H. Kawakita, and H. Tanimoto, xe2x80x9cHigh-Frequency Device-Modeling Technique for RF-CMOS Circuits,xe2x80x9d IEICE Trans. Fundamentals., vol. E84-A, no. 2, pp. 520-528, February 2001).
FIG. 10A is a plan view showing the pad structure used for the input/output port of the conventional semiconductor integrated circuit device. FIG. 10B is a sectional view taken along the line Exe2x80x94E. Referring to the Figures, the reference numeral 100 designates a silicon substrate, the numeral 102 designates an interlayer insulation film made,of oxide film, the numeral 103 designates a pad made of a metal layer, and the numeral 104 designates an device-isolation made of oxide film, abbreviated as STI (Shallow Trench Isolation).
The operation will next be described below.
Formation of a pad 103 by use of metal (metal layer) on the insulation film 102 and the device-isolation 104 formed over the silicon substrate 100 forms parasitic capacitance Cp with the device-isolation 104 and the insulation film 102 as an interlayer film, and the formation develops the resistance component Rsub of the silicon substrate 100 in series with the parasitic capacitance Cp. In the device, when a high frequency signal is applied on the pad, the parasitic resistance Rsub in the resistance components thereof can become a factor of the signal loss and the heat noise.
FIG. 11 is a plan view showing another pad structure of a conventional semiconductor integrated circuit device. The figure illustrates a pad used for the input/output port of a semiconductor device in the recent semiconductor microfabrication process. The structure of FIG. 11 differs from that of FIG. 10A and FIG. 10B in that an active region 106 in the transistor structure is disposed also right under the metal of the pad 103. The active region 106 becomes a dummy active region in contrast to active elements such as transistors used for the circuit located in close vicinity to the pad.
In other words, the dummy active region has the job of increasing the planarity (flatness) of the area very close to the pad when planarizing the surface of the substrate by means of CMP (Chemical and Mechanical Polishing). Thereby, finished quality consistency from transistor to transistor disposed adjacent to the dummy active region improves. The planarization of the semiconductor substrate is described in the following conventional example (see A. Chatterjee, M. Nandakumar, S. Ashburn, V. Gupta, P. Kwok, and I.-C. Chen xe2x80x9cOn Shallow Trench Isolation for Deep Submission CMOS Technologies,xe2x80x9d Extended Abstracts of the International Conference on Solid State Devices and Materials, A-8-1, pp. 288-289, 1998).
A model circuit shown in lumped constants corresponding to the conventional pad structure will next be shown in FIG. 12. Referring to FIG. 12, Cp shows a parasitic capacitance caused between metal constituting the pad and silicon substrate, and Rsub and Csub show a resistance component and a parasitic capacitance of the silicon substrate, respectively. In this model circuit, the resistance component Rsub is a factor of the signal loss. When a high frequency signal is applied on the pad, the parasitic resistance loses the signal.
Since the conventional semiconductor integrated circuit device is arranged as mentioned above, in most cases a floating active region exists or never exists just under the metal layer of the pad or wiring. There has been a drawback that the loss of the signal is larger in a high-frequency region because of the existence of the parasitic resistance component Rsub caused by the metal layer in the equivalent circuit.
The present invention has been accomplished to solve the above-mentioned problem. An object of the present invention is to provide a semiconductor integrated circuit device in which the signal loss is reduced in a signal line or spiral inductor formed by a pad or metal in a high-frequency region, and the CMP planarity in the semiconductor microfabrication process is improved.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device including: a semiconductor substrate including a silicided active region formed on the main surface thereof and a non-active region provided by device-isolation on the same surface; an interlayer insulation film formed on the substrate; and a conductor pad formed in a predetermined-patterned shape on the insulation film, wherein a shield/planarization portion in which the area ratio of the active region to the non-active region is given in a predetermined proportion and the active region is electrically grounded is disposed between the semiconductor substrate and the insulation film just under the pad.
Thus, the CMP planarity is increased by means of properly selecting the area ratio and further the parasitic resistance component Rsub of the substrate can be minimized by means of ground-shielding the active region. Therefore, the consistency in the completed quality of the transistors located around the pad and further the signal loss is reduced when applying the high frequency signal on the pad.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device including: a semiconductor substrate including a silicided active region formed on the main surface thereof and a non-active region provided by device-isolation on the same surface; an interlayer insulation film formed on the substrate; and a conductor wiring layer formed in a predetermined-patterned shape on the insulation film, wherein a shield/planarization portion in which the area ratio of the active region to the non-active region is given in a predetermined proportion and the active region is electrically grounded is disposed between the semiconductor substrate and the insulation film just under the wiring layer.
Thus, the proper selection of the area ratio can increase the CMP planarity and further the ground shield of the active region can minimize the parasitic resistance component of the substrate. Therefore, the consistency in the completed quality of the transistors located around the wiring layer can be increased and the signal loss can be reduced when applying a high frequency signal on the wiring layer.
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device including: a semiconductor substrate including a silicided active region formed on the main surface thereof and a non-active region provided by device-isolation on the same surface; an interlayer insulation film formed on the substrate; and a conductor inductor formed in a predetermined-patterned shape on the insulation film, wherein a shield/planarization portion in which the area ratio of the active region to the non-active region is given in a predetermined proportion and the active region is electrically grounded is disposed between the semiconductor substrate and the insulation film just under the inductor.
Thus, the proper selection of the area ratio can increase the CMP planarity and further the ground shield of the active region can minimize the parasitic resistance component of the substrate. Therefore, the consistency in the completed quality of the transistors located around the wiring layer can be increased and the signal loss can be reduced when applying a high frequency signal on the wiring layer.